1. Field of the Invention
The present invention relates to a semiconductor device, particularly to a semiconductor device in which shallow trench isolation (STI) is formed for element isolation.
2. Description of Related Art
In order to highly integrate a semiconductor device, STI is employed which can provide a narrow element isolation region. However, a problem is pointed out that a divot (a groove-like step or a dimple) is generated in a dielectric film buried in a trench.
Japanese Laid Open Patent Application (JP-P2000-323563A) discloses a manufacturing method of semiconductor device for preventing the generation of divot. In this manufacturing method, an oxide film is formed on a silicon substrate, an antioxidation film such as a silicon nitride film is formed on the oxide film, a trench for element isolation is formed in the silicon substrate through the antioxidation film and the oxide film, and a dielectric film is formed to be buried in the trench after retreating the antioxidation film by isotropic etching. The antioxidation film is used as a stopper for chemical-mechanical polishing (CMP) of the dielectric film. After the CMP, the antioxidation film is removed and wet etching is applied to the oxide film. In this manufacturing method, since the dielectric film is formed after the retreat of the antioxidation film, the dielectric film is formed on also a portion of the oxide film exposed by the retreat. As a result, the portion of the oxide film under the dielectric film is prevented from being removed in the wet etching and generation of divot is prevented in the dielectric film buried in the trench.
Japanese Laid Open Patent Application (JP-P2003-77934A) discloses an oblique impurity implantation. In the oblique implantation, impurity of the same type as a substrate impurity is implanted in the oblique direction into a substrate with a gate being used as a mask. The oblique implantation can effectively prevent a short channel effect.
The present inventor has recognized as follows.
When the above mentioned process of forming the dielectric film after the retreat of the antioxidation film is applied to manufacture of a semiconductor device including a memory cell region in which memory cells are formed and an outside of the memory cell region, there is a possibility that the following problems are caused. In general, a distance between trenches for element isolation is wider in the outside of the memory cell region than in the memory cell region. Therefore, width of a portion of an antioxidation film above a portion of a silicon substrate between the trenches is narrow in the memory cell region and wide in the outside of the memory cell region. Here, the distance between the trenches corresponds to channel width of a transistor. When the antioxidation film is retreated, a ratio (W1/W2) of width (W1) of the portion of the antioxidation film in the memory cell region relative to width (W2) of the portion of the antioxidation film in the outside of the memory cell region is decreased. Therefore, when impurity for adjusting a threshold voltage of the transistor is implanted into the silicon substrate from a opening formed by removing the antioxidation film, an implantation condition for achieving a proper amount of implanted impurity in the outside of the memory cell region may cause an insufficient amount of implanted impurity in the memory cell region. That is, although the generation of divot can be prevented by forming the dielectric film after the retreat of the antioxidation film, it is difficult to adjust the threshold voltage of the transistor to be a desired value in both the memory cell region and the outside of the memory cell region.